In the electronics industry, semiconductor devices with the ability to operate at relatively faster speeds are increasing in demand with the development of higher performance electronic systems.
The development of synchronous dynamic random access memory (SDRAM) devices resulted in improvements in the relative operation speed of the DRAM devices. SDRAM devices typically operate in synchronization with an external clock signal. An example of an operation that may be executed in a SDRAM device is a burst operation. In a burst operation data corresponding to a burst length are successively input in response to a write command signal and successively output in response to a read command signal in accordance with a burst length set by a mode register set (MRS). The burst length of the data for the burst operation may be “4”, “8”, “16”, or “32” bits in length. For example, if the burst length is “16”, sixteen bits of data may be successively input in response to a write command signal and successively output in response to a read command signal.
At least two semiconductor devices may communicate with each other via electrical signals. If a specific signal is applied to a first semiconductor device of the at least two semiconductor devices, an operation corresponding to the specific signal may be executed in the first semiconductor device after a predetermined period of time following the receipt of the specific signal at the first semiconductor device. The predetermined time is referred to as latency. For example, a time period extending from the receipt of a read command signal at the first semiconductor device till the output of data from the first semiconductor device in response to the read command signal may be referred to as a column address strobe (CAS) latency, and a time period extending from the receipt of a write command signal at the first semiconductor device till the input of data to the first semiconductor device may be referred to as a write latency period (WL).